Programmable logic devices (PLDS) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (ASICs) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs may include blocks of smaller logic elements (LEs) which typically have a number of inputs. The blocks containing LEs are sometimes referred to as logic array blocks (LABs; also referred to by other names, e.g., configurable logic blocks, or CLBs). LEs, in turn, may contain components to programmably carry out different types of logic functions. LABs containing LEs may be arranged in a two dimensional array in a PLD.
In order to input and direct logic signals to LEs, PLDs can include a number of types of signal lines. A first type of line, referred to herein as a global line, can carry signals between LABs. Other lines can be driven by global lines to carry signals into a particular LAB. These lines are referred to herein as LAB lines (LAB lines can also be referred to as logic input MUX or “LIM” lines). LAB lines 14 typically include between 20 to 40 individual lines, though greater or fewer lines may also be included. The architecture of a LAB may also include LE output lines which can be routed back to drive the inputs of either the LE that drove the particular output or a different LE, typically within the same LAB. Thus, it is not necessary, and typically not the case, that a LAB is driven by enough LAB lines to drive every input of every LE in the LAB.
However, it is sometimes that case that a logic function which could otherwise be carried out by a single LAB cannot be because the particular logic function requires more inputs into the lab than are provided by the LAB lines. In such a case, in configuring a PLD to carry out the logic function, it may be necessary to split the logic function between two or more LABs in the PLD. Such configuration, though, can cause inefficient use of physical resources and increased timing delays.